星期五, 5月 08, 2009

EE3120 (B) MP & ASSEMBLY LANGUAGE PROG (02EE3120) Assignment 2 Solution

Assignment 2 Solution 2008/9
Question 1 (34 marks)

Answer 1(a)(i)In asynchronous serial transmission, the transmitter's clock and receiver's clock are not synchronized. In order toreceive data correctly, it is necessary to define a protocol on how the data are packed, how many bits constitute acharacter, and when the data begins and ends. Generally, this is done by placing a character between start and stopbits as shown in the following figure. This is called framing.Framing ASCII “A”(41H)When a start bit is received, the receiver will delay a fixed amount of clock cycles which is roughly equal to thehalf period of the data bit width, then sample the data line at roughly the middle of the data bit. If the clockfrequencies for the transmitter and receiver ends are close enough, this provides highly reliable data reception.However, both parties must agree upon the same number of data bits and parity bits in a frame.[5 marks]Answer 1(a)(ii)In 8-bit UART variable mode, the shift clock is derived from the system (x'tal frequency) clock through a series ofdividers shown in the figure below. First the system oscillating frequency will be divided by 12. Timer 1 whichhas to be programmed into 8-bit auto reload model is the second stage of clock division. The dividing constant isdetermined by the value stored in TH1 register. The overflow clock is further divided by 2 if the SMOD bit in thePCON register is 0, otherwise no division is result. Finally, the clock will be divided by 16 before entering into theserial port shift clock. The baud rate can be computed according to the formula:Baud rate =2SMOD32 12 (256-TH1)osc × f× ×Assuming system clock is 11.0592MHz and SMOD=0, for a value of TH 1=253 (i.e., -3 in 8-bit sign integer), thebaud rate is20 11.0592 10632 12 (256-253)× ×× × =9600[6 marks]Answer 1(a)(iii)Main:Continue:Wait:Forever:Sting:Answer 1(b)(i)ORG 0200HMOV DPTR, #StringMOV TMOD, #20HMOV THl,#-24MOV SCON, #50HSETB TR1CLR AMOVC A, @A+DPTRJZ ForeverMOV SBUF, AJNB TI, WaitCLR TIINC DPTRSJMP ContinueSJMP ForeverORG 0400HDB "City University of Hong Kong", 0END; load DPTR with String address; Timer 1, 8-bit auto reload; 1200 baud; 8-bit UART variable; start Timer 1; Read character of Sting»; write to serial port; wait for TI to set; wait TI; increase pointer; continue to transmit next char; do nothing[8 marks]Vector-table approach to interrupt handling is to assign a fixed location in program memory for storing the jumpvector for each interrupt source. When an interrupt happens, processor will finish the current instruction and savethe PC value on stack and then jump to the corresponding location according to the interrupt source. Generally, ajump instruction to the starting address of the interrupt service routine (ISR) will perform. In the case of 8051,there are six interrupt sources including RESET. We can place a LJMP ISR_Address instruction in thecorresponding location. For example, the following instructions put a jump vector for timer 0 interrupt:ORG 0000BHLJMP Timer1_ ISRTimerl1_ISR:ORG 0100H............RETISince the gap between interrupt vectors (except RESET) is eight bytes, we can put the interrupt service routinedirectly in the jump vector location if the size of its ISR is less than or equal 8 bytes. This helps to speed upinterrupt handling for fast real time response.Interrupt ROM Location (Hex) Pin[5 marks]Flag ClearingReset 0000 9 AutoExternal hardware interrupt 0 (INTO) 0003 P3.2(12) AutoTimer 0 interrupt (TFO) 000B AutoExternal hardware interrupt 1 (INT1) 0013 P3.3(13) AutoTimer 1 interrupt (TF1) 001B AutoSerial COM interrupt (RI and TI) 0023 Programmer clears it.Answer 1(b)(ii)ORG 0000H ; Reset vectorLJMP Main;ORG 000BH ; Timer 0 interrupt vectorCPL P2.1 ; toggle P2.1 for square wave outputRETI ; return from ISR;ORG 0023H ; Serial port interrupt vectorLJMP Serial ; jump to serial ISRRETIMain: ORG 0030HMOV P1,#OFFH ; make P1 an input portMOV TMOD, 22H ; timer 0 and 1 are 8-bit auto reloadMOV TH1,#-12 ; 1200 baud rateMOV SCON, #50H ; 8-bit UART with REN enableMOV THO, #-46 ; period for 10 kHz square waveMOV IE, #92H ; enable serial and timer 0 interruptsSETB TR1 ; start timer 1SETB TRO ; start timer 0Back: MOV A, P1 ; read data from Port 1MOV SBUF, A ; write it out to serial portSJMP Back ; loop indefinitely;ORG 0100H ; serial ISR locationSerial: JB TI, Trans ; jump if tx interrupt otherwise rxinterruptMOV A, SBUF ; get the received dataMOV P0,A ; and write it to P0CLR RI ; clear RI (non auto-cleaning)RETI ; return from ISRTrans: CLR TI ; clear TI (non auto-cleaning)RETI ; return from ISREND[10 marks]Question 2 (34 marks)Answer 2(a)ALE is the address latch enable signal output from the 8051 family of microcontrollers. It is a pulse for latching the low-order byte of taccesses to external memory or I/O. Because the low-order byte address (AO-A7) is time-multiplexed with the data (DO-D7) on the phyAD7). A latch, e.g. 74LS373, can be used to latch the address (AO-A7), while data bus (DO-D7) will be available after the addrefollowing circuit can be used. The advantage of using multiplexed bus in 8051 is to save a number of physical pin sfor the chip to codevices. However, by doing so, the speed of external access will be reduced because address and data are multiplexed on the sameaddress has to be latched first, then come the data.[6 marks]Answer 2(b)(i)ROM with an address range 0000 - 3FFF has a size of 16 kbytes. EPROM with an address range 0000 -1FFF has a size of 8 kbytes; RAM with an address range COOO - DFFF has a size of 8 kbytesROM chip required is 1 EPROM chip required is 1 RAM chiprequired is 2[5 marks]Answer 2(b)(ii)[11 marks]Answer 2(b)(iii)

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